Vibe-IC

Three-phase flow — Prompt to Chip

Every IC starts from a user-friendly dialogue and ends with a verified chip on FPGA.

No technical jargon — AI translates your product needs into silicon.

Spec — Dialogue → Design Documents

What users can understand

PM Agent talks to you in plain language
7 tradeoff questions (compatibility, power, cost...)
IC Expert Agent reviews for completeness
Every decision traceable to your answer

Deliverable: input/ folder + Design documents

Design — Documents → RTL → FPGA PASS

What engineers can understand

Path A (from prompt): Phase 1 emits L1-L13 directly → straight to 2b (skips 2a)
Path B (from existing spec docs): 2a deterministic doc-gen → L1-L13
2b: L1-L13 → RTL — both paths converge here
Verification: lint → simulation → formal → FPGA compile → hardware test
350 deterministic programs ensure reproducible results

Deliverable: RTL + SOF + test reports

Silicon — RTL → GDS → Signoff

What the foundry needs

Synthesis → 3-corner STA (SS/TT/FF) → P&R → GDS
Signoff: DRC / LVS / PERC / IR-drop / EM / ATPG
GF180 / SKY130 (open) + custom PDK support
Tapeout checklist → submit to foundry

Deliverable: GDS + DRC/LVS/STA reports

Dual Organic Growth — Standing on Giants

An organic plugin built on the world's strongest AI. General skills grow as the AI giant grows. Domain expertise deepens through community contributions.

The AI Giant Grows

General skills — automatic

Built on the world's most capable AI (Claude) — not our own model
As the AI improves reasoning, coding, hardware knowledge — all 50 unified skills automatically produce better results
Zero effort from us — the platform lifts everything

We ride the giant. As it grows, we grow.

The Opensource Community Deepens

Domain expertise — community-driven

Every agent using the plugin can contribute back — when a bug is found, the agent asks: "What general gate would catch this class?"
350 deterministic programs accumulate from real-world experience — each one prevents an entire class of bugs
IC design domain expertise that the AI alone doesn't have — encoded as code, not prompts

The plugin gets more professional with every contribution.

Open to Everyone

Open to everyone — plugin your device, your IP, your knowledge.

Plugin Your Device

FPGA boards, testers, scopes, lab equipment

Drop a manifest.json in src/devices/ — your device becomes an MCP tool instantly
FPGA boards, protocol testers, oscilloscopes, logic analyzers
Zero server code changes — the MCP server auto-registers new devices

Any hardware vendor can join the ecosystem

Plugin Your IP

Reusable IP blocks for the community

Contribute verified, reusable IP blocks (I2C slave, SPI master, UART, CRC engines, FIFO, arbiters...)
Extract small, independent IP from open-source ICs into the community database
Plugin users call these IPs directly — no need to regenerate common building blocks

IP providers can reach every Vibe-IC user

Plugin Your Knowledge

Community backlogs that evolve the plugin

When your agent finds a bug, it reviews the plugin: "What general gate would have caught this?"
Enhancement opportunities (not bugs) are recorded as IC-agnostic backlogs — no vendor data, no secrets
EDA tool vendors, foundries, design houses — anyone with IC design knowledge can contribute

Every user makes the plugin smarter for everyone

MCP EDA Server

Model Context Protocol is the wire between Claude and the silicon stack. We open-sourced an MCP server that exposes 46 tools — synthesis, place & route, GDS export, FPGA programming, scope capture, protocol testing, SPICE corner sweep, analog layout, xschem netlist, ADC read, oracle dump — as one declarative interface.

What is MCP?

A protocol, not a framework

Model Context Protocol — open standard from Anthropic, JSON-RPC over stdio
Three primitives: tools (do something), resources (read state), prompts (templates)
Vendor-neutral — works with Claude Code, Claude Desktop, any MCP client
Decouples agent reasoning from tool execution

One protocol, any model, any tool

What we built

mcp-eda-server v0.114.0 — 46 tools

37 EDA tools: lint, synth, sim, formal, PnR, GDS, STA, DFT, LVS, DRC, IR drop, FPGA compile, SPICE corner sweep, xschem netlist, analog layout, oracle dump, ...
9 device tools: scope capture/measure, FPGA program/detect/ADC read, MD-905 USB-HID tester, ID-bus opcode injector, camera LED diff
Live MCP resources: scope://current_setup, fpga://board_status
Wraps IIC-OSIC-TOOLS Docker — open-source EDA in one image

Open source, any one, any agent

Why it matters

Self-healing diagnostics + anti-fabrication

No silent PASS — every tool failure surfaces actionable hints
Auto-recover: docker-group self-heal, DRT-0073 PnR retry, layermap auto-discovery
Provenance logged: every call records {tool, version, input/output hash, exit, duration}
Pre-flight eda_doctor + post-build eda_pdk_lint catch broken setups before tapeout

Tools you can trust mid-tapeout

50 AI Skills

Each skill is a domain expert guiding one step of the IC design flow.

Phase 1 — Path A: Prompt / Dialogue → L1-L13 → straight to Phase 2b (skips 2a)

phase1spec-reviewpm-agentic-expert-agent

Phase 2a — Path B only: existing spec docs → L1-L13 (deterministic doc-gen)

phase2a-output-verify

Phase 2b — Both paths converge: L1-L13 → RTL → Verification → FPGA PASS

rtl-reviewrtl-repairformal-verifyequivalence-checkregression-managecheckpoint-gatespec-validatorppa-predicthls-c2rtlarchitecture-explorefpga-hps-bridgefpga-signaltapfpga-led-probe-allocationhw-debug-loopprotocol-timeline-assertprotocol-turnaround-auditscope-pattern-attestationcompliance-gate-spot-checkphase2b-rtl-verifycommunity-backlog-submit

Analog Track — A1-A8: Spec → SPICE → Layout → Hardmacro → Co-Sim

analog-spec-extractanalog-topology-selectanalog-sizinganalog-sizing-loopanalog-netlist-genanalog-layoutanalog-extraction-resimanalog-hardmacro-genanalog-hw-testbench-genanalog-hw-measureanalog-hw-tuning-loopanalog-flow-orchestrateanalog-output-verifymixed-signal-cosim

Phase 3 — Silicon: RTL → GDS → Signoff

synth-doctorsta-reviewhold-fixdrc-fixlvs-triageir-drop-triageeco-plantapeout-checklistatpg-name-harmonizeams-simyield-diagnosticphase3-backend-verify

350 Deterministic Programs

Layer 1: compliance.yaml regex checks agent output text.
Layer 2: programs verify actual artifacts.
Layer 3: MCP execution proof + provenance hash match.
Layer 4: real-hardware pass attestation (L13).

RTL pattern auditors

fsm_error_invariantrtl_hygiene_lintrx_tolerance_sweepphy_counter_auditoe_pattern_checkinterface_encoding_auditcrc_bitorder_checktristate_self_rx_mask_checkpulse_decoder_edge_checkpacket_length_check_presentotp_write_lock_gate_checkl12_sequence_implementation_checktimer_freeze_after_state_checksustained_vs_edge_checktransient_signal_latch_checkfpga_pullup_lintself_rx_mask_checkfpga_async_input_synchronizer_checkfpga_wrapper_input_polluter_checkderived_clock_sdc_required_checkperiodic_signal_required_checkmask_application_checkpayload_bit_position_checkrom_init_lintpre_awake_silence_checkcrc_engine_isolation_checkbit_count_modulo_checkcmd_arg_range_validation_checkresponse_payload_template_checkdispatcher_tx_arm_order_checkdispatch_fetch_loop_population_checkdispatch_register_default_reset_checkhost_soft_reset_unwake_path_checkrig_topology_disclosure_checkdispatcher_response_size_table_auditdispatcher_awake_gate_checkpad_drive_high_active_checkbreak_framing_vs_l3_checkbreak_handler_safety_checktx_abort_during_transmission_check

Spec-RTL coherence — Phase-2a

internal_vs_external_timing_checkrsp_example_otp_consistency_checkthreshold_range_contiguity_checkspec_response_delay_checknba_addr_read_race_checkperiodic_timer_vs_rx_activity_checkmemory_read_pipeline_checkprotocol_delimiter_consistency_checkcross_constant_invariant_checkno_protocol_consistency_checkcrc_seed_consistency_check

Design artifact check

constants_validationintegration_spec_auditassertion_property_checksynth_wrapper_checksdc_syntax_checkupf_syntax_checkmodule_port_auditcorner_coverage_audit

Backend report audit

drc_report_checklvs_report_checkpower_report_checkem_report_checkir_drop_report_checksta_report_checksynth_netlist_checkgds_size_check

Phase-1 extraction + consistency

phase1_doc_presence_checkphase1_consistency_checkphase1_k5_quality_checkphase1_quality_parity_checkphase2a_gate_contract_checkmanifest_leak_checkxlsx_extractdoc_extractcmd_protocol_crc_verifyclock_scale_consistency_checklayer_extension_presence_checkinput_docs_coverage_check

Anti-fabrication + provenance

def_stage_progression_checkprovenance_loggerprovenance_checkfpga_on_board_attestation_checkhardware_pass_attestation_checkfresh_agent_provenance_checkwaivers_schema_checkfpga_verification_auditrtl_bug_report_schema_checkfpga_program_chain_attest_checkmcp_execution_verifygate_evidence_completeness_check

Flow orchestration

flow_compliance_checkstage1_compliancestage2_compliancestage3_compliancestage4_complianceflow_stage_checktapeout_signoff_checksignoff_auditrelease_auditfoundry_signoff_plan_checkwaiver_growth_check

Functional close-loop + debug

cmd_response_conformance_checkfault_atpg_runquartus_map_auditbist_window_calculatorbit_level_full_stack_tb_checkverilator_coverage_measurertl_precheck_gatescope_periodic_pulse_checkfunctional_state_transition_coverage_checktrailing_delimiter_completeness_checkrtl_unit_test_coverage_checkl10_tb_conformance_checkl12_tb_coverage_checktester_oracle_health_checkbehavioral_evidence_per_spec_item_check

Protocol / CRC / bring-up

crc_residual_checkgap_reset_granularity_checkdevice_response_no_br_checkbitwidth_consistency_checkcrc_completeness_checkhandshake_checkprotocol_gap_checktristate_bus_checkcdc_async_input_checkreset_dependency_checkcrc_vector_genhw_vs_rtl_verdict_check

Analog pipeline gates

analog_block_coverage_checkanalog_corner_sweep_checkanalog_netlist_pdk_checkanalog_hw_spice_correlation_checkanalog_hardmacro_checkmixed_signal_cosim_checkanalog_pre_vs_post_layout_checkanalog_flow_compliance_checkanalog_digital_interface_check

EDA / FPGA infrastructure gates

cdc_crossing_checkcoverage_metric_checksv_compat_checkpdk_consistency_checkfpga_qsf_linttestbench_exists_checkl9_completeness_checkjson_schema_checkeda_log_checkeda_report_auditoutput_artifact_checkotp_image_check

Marketplace / plugin lifecycle

practical_notes_specificity_checkskill_compliance_triangle_check

OpenROAD / Yosys lint

openroad_tcl_deprecation_checkyosys_hilomap_required_checkyosys_script_template_check

Quick install

Four steps. The Docker image (~22 GB) bundles every EDA tool. Hardware lab is optional — simulation and GDS tapeout flows do not need physical devices.

Pull EDA Docker + run container

docker pull hpretl/iic-osic-tools:latest

docker run -d --name iic-eda \
  -v $HOME/designs:/design \
  hpretl/iic-osic-tools:latest --wait

--wait keeps the container alive so MCP can docker exec into it.

Clone + register MCP EDA server

git clone https://github.com/reyerchu/\
  AI_IC_design.git
cd AI_IC_design/mcp-eda-server
npm install

claude mcp add eda-tools \
  node $(pwd)/src/index.js \
  -e EDA_CONTAINER=iic-eda

Verify with claude mcp list — eda-tools should be listed.

Add marketplace + install vibe-ic plugin

# start an interactive Claude session
claude

# inside the session, run two slash commands:
> /plugin marketplace add \
    /path/to/AI_IC_design/vibe-ic-marketplace

> /plugin install vibe-ic@vibe-ic-marketplace

/plugin commands run inside Claude Code — not in your shell.

Start designing

claude "Design a temperature sensor IC
        with I2C interface, 12-bit,
        alert output, SOIC-8 package"

Or invoke directly: /vibe-ic-all

Need full troubleshooting? See mcp-eda-server/INSTALL_GUIDE.md for prerequisites, Docker / Node / Quartus setup, and step-by-step verification.

Hardware Lab (optional)

Physical devices for FPGA bring-up and on-board verification. Not required for simulation or GDS tapeout flows.

FPGA Board — Terasic DE10-Lite

# 1. Install Quartus 23.1 Lite (free)
#    intel.com/Quartus → Lite Edition
# 2. USB-Blaster udev rule
sudo cp quartus/linux64/51-usbblaster.rules \
  /etc/udev/rules.d/ && sudo udevadm control --reload
# 3. Tell MCP server where Quartus lives
#    Edit .claude/.mcp.json → env:
"QUARTUS_ROOTDIR": "/path/to/quartus",
"PATH": "/path/to/quartus/bin:..."
# 4. Verify: restart claude, then run
#    eda_device_list → quartus_pgm: satisfied

Oscilloscope — Keysight InfiniiVision

# No driver needed (Linux USB TMC built-in)
# 1. Plug in scope via USB
# 2. Grant permission
sudo usermod -aG plugdev $USER
# 3. Verify: log out/in, then
lsusb | grep 2a8d
# 4. Restart claude → eda_device_list
#    → scope: plugdev satisfied

Want to ship your own device, IP, or partner plugin? See the Open Platform page.

Design chips withnatural language