Open Platform — Vibe-IC

01 Device Hardware

Lab instruments — scopes, FPGAs, testers, cameras, logic analyzers, signal generators, power supplies, DMMs. Drop a folder, the server auto-registers every tool you declare.

Folder layout

mcp-eda-server/src/devices/
└── <category>/
    └── <vendor-device>/
        ├── manifest.json     # required
        ├── driver.py         # required (stdin JSON / stdout JSON)
        ├── README.md         # required
        ├── udev/*.rules      # optional
        └── tests/            # recommended

# 13 canonical categories:
fpga · scope · tester · camera ·
logic-analyzer · fgen · dcpwr ·
acpwr · dmm · specan · rfsiggen ·
swtch · pwrmeter · counter

Manifest schema

{
  "vendor": "keysight",
  "device_class": "oscilloscope",
  "ivi_class": "IviScope",
  "supported_platforms": ["linux"],
  "permissions": ["require_group:plugdev"],
  "tools": [{
    "name": "device_scope_capture",
    "description": "Capture a window from the scope.",
    "driver": "driver.py",
    "tool_mode": "capture",
    "mode": "hw",
    "timeout_sec": 60,
    "schema": {
      "channel": {"type":"integer","default":4},
      "span_ms": {"type":"number","default":50},
      "trigger": {"type":"string","enum":["rising","falling"]}
    }
  }],
  "resources": [/* optional MCP resources */]
}

Reference: Terasic DE10-Lite (3 tools), Keysight DSO-X (2 tools), Noirs MD-905 (4 tools). All auto-registered by src/devices/_registry.js at server start.

02 EDA Tool

Software tools — Yosys, OpenROAD, KLayout, SymbiYosys, OpenSTA, ngspice, Magic, Verilator, iverilog, xschem, Xyce, cocotb, Fault, Netgen. Core tools execute inside the IIC-OSIC-TOOLS Docker image (TU Wien).

Where 37 EDA tools live

mcp-eda-server/src/index.js
├── server.tool("eda_lint", ...)
├── server.tool("eda_synth", ...)
├── server.tool("eda_simulate", ...)
├── server.tool("eda_formal", ...)
├── server.tool("eda_pnr", ...)
├── server.tool("eda_gds", ...)
├── server.tool("eda_sta", ...)
├── server.tool("eda_drc_klayout", ...)
├── server.tool("eda_lvs", ...)
├── server.tool("eda_ir_drop", ...)
├── server.tool("eda_spice", ...)
├── server.tool("eda_fpga_compile", ...)
└── ... (37 total)

# Single Docker image
hpretl/iic-osic-tools:latest

Add a partner-specific tool

# Don't fork core. Use the same manifest
# contract as a device — but pointing at
# your own EDA binary or shell script.

partner-acme-synth/
└── mcp-eda-server/src/devices/
    └── synth/acme-syn-pro/
        ├── manifest.json
        ├── driver.py     # invokes your tool
        └── README.md

# manifest.json declares tools[] just like
# any device — auto-registered at startup.
# Core src/index.js never changes.

Cross-PDK: GF180MCU (180nm) + SKY130 (130nm) + custom PDK paths via pdk_local/<vendor>/

03 IC IP Block

Reusable verified IP blocks — UART, SPI, I2C, CRC engines, FIFO, arbiters, FSMs. Each contribution carries metadata + RTL/macro deliverable + a list of historical bug classes the IP has seen, so future agents borrow the lesson.

Folder layout

vibe-ic-marketplace/
└── reference-plugins/
    └── <your-ip>/
        ├── ip_metadata.yaml   # required
        ├── plugin.yaml        # plugin manifest
        └── files/             # RTL · macro · netlist
            ├── rtl/
            ├── lef/
            ├── gds/
            └── lib/

# Reference (already shipped):
reference-plugins/example-ip/
└── tiny-uart (8-N-1, MIT)

ip_metadata.yaml schema

ip_id: tiny-uart
vendor: example-org
license_tag: open-source-mit
deliverable_kind: soft-ip   # or hard-ip

interface:
  bus: APB-like
  data_width: 8
  clock_domain_required: single
  reset_polarity: active-low

constraints:
  max_freq_mhz: 50
  pdk: any   # any | sky130 | gf180mcu | ...

known_issues: []
historical_failure_modes:
  # bug classes this IP has seen — for
  # future agents to borrow the lesson
  - "Baud divider must be set before TX"
integration_notes:
  - "Simple 8-N-1 UART; no flow control."

04 Partner Plugin

One bundle for vendors who want to ship the full stack: slash commands, NL skills, deterministic gates, MCP device drivers, and foundry-specific PDK files — all in a single plugin folder.

Skeleton layout

vibe-ic-marketplace/templates/
└── partner-plugin-skeleton/
    ├── .claude-plugin/
    │   └── plugin.json     # name · version · author
    ├── commands/           # slash commands (optional)
    │   └── <your-command>.md
    ├── skills/             # NL skills (optional)
    │   └── <your-skill>/SKILL.md
    ├── programs/           # deterministic Py (optional)
    │   └── <your-class>_check.py
    ├── mcp-eda-server/     # device drivers (optional)
    │   └── src/devices/<class>/<vendor>/
    │       ├── manifest.json
    │       └── driver.py
    ├── pdk_local/<vendor>/ # foundry PDK (optional)
    │   ├── liberty/
    │   ├── lef/
    │   ├── gds/
    │   ├── drc/
    │   └── lvs/
    └── README.md

Registration steps

# 1. Copy the skeleton
cp -r vibe-ic-marketplace/templates/\
  partner-plugin-skeleton \
  vibe-ic-marketplace/plugins/\
  partner-<vendor>-<topic>

# 2. Edit .claude-plugin/plugin.json
{
  "name": "partner-acme-i2c-ip",
  "version": "0.1.0",
  "author": "ACME Semiconductor",
  "description": "I2C master/slave IP + ..."
}

# 3. Add one entry to root marketplace.json
{
  "plugins": [
    ...,
    { "name": "partner-acme-i2c-ip",
      "path": "plugins/partner-acme-i2c-ip" }
  ]
}

# 4. Open a PR
git push origin partner-acme-i2c-ip
gh pr create

Audience: EDA vendors · foundries · IP houses · design service companies. Each can ship its full domain expertise without forking core.

05 Community Backlog

When an agent finds a bug in real silicon, it must NOT just patch the bug. It must look back at the plugin and ask: What general gate would catch this whole class of bugs? That answer — the enhancement opportunity, IC-AGNOSTIC — gets recorded back to the community. The plugin gets professional with every contribution.

The generality rule (NON-NEGOTIABLE)

✅ Record (enhancement)	❌ Skip (specific bug)
"Plugin lacks a gate for protocols where CRC init / update happen on the same cycle"	"Our IC's CRC output is wrong because crc_init and crc_update overlap"
"No program checks that wake signals have ≥2 clear paths"	"Wake register only clears on rst_n, missing soft-reset"

Sanitize automatically: chip names → "a cable-side ID IC"; vendor names → "the vendor"; OTP hex dumps → "OTP content".

Submit flow

# Inside an active design session, invoke
# the skill (Claude Code handles it):

claude "use community-backlog-submit
        skill to record this gap"

# The skill writes:
vibe-ic-marketplace/community/backlogs/
└── <class-tag>.yaml

# backlog_sanitize_check.py auto-strips:
#   - chip names (regex from K1 class_kb)
#   - vendor names
#   - OTP hex dumps
#   - vendor PDF filenames

# Then the skill emits a PR-ready diff;
# you review and submit.

# A passing sanitize-check is REQUIRED
# for the PR to merge — chip-AGNOSTIC
# is enforced by code, not honor system.

Plug in your device,
your IP, your knowledge.

Platform architecture

01 Device Hardware

Folder layout

Manifest schema

02 EDA Tool

Where 37 EDA tools live

Add a partner-specific tool

03 IC IP Block

Folder layout

ip_metadata.yaml schema

04 Partner Plugin

Skeleton layout

Registration steps

05 Community Backlog

The generality rule (NON-NEGOTIABLE)

Submit flow

Submit a contribution

Plug in your device,your IP, your knowledge.

Platform architecture

01 Device Hardware

Folder layout

Manifest schema

02 EDA Tool

Where 37 EDA tools live

Add a partner-specific tool

03 IC IP Block

Folder layout

ip_metadata.yaml schema

04 Partner Plugin

Skeleton layout

Registration steps

05 Community Backlog

The generality rule (NON-NEGOTIABLE)

Submit flow

Submit a contribution

Plug in your device,
your IP, your knowledge.